本文描述两种高密度MOS联想存贮器单元的设计。第一种单元适合于数据管理应用,具有三种内部状态,包括不管(屏蔽)条件。第二种单元适合于并行处理应用,具有被选位写数的能力。两种单元都占用大约20密耳的硅片面积,允许在一个芯片上实现512位。采用可变电抗器自举作用来提高存贮结点电压以改进单元工作。对于使用相容的双极晶体管进行了讨论。 This article describes the design of two high-density MOS associative memory cells. The first unit is suitable for data management applications and has three internal states, regardless of (masked) conditions. The second unit is suitable for parallel processing applications, with the ability to be selected bit write number. Both units occupy about 20 mils of silicon area, allowing 512 bits on a single chip. The use of varactors to boost the storage node voltage to improve cell work. The use of compatible bipolar transistors is discussed.