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通过对相位插值器电路进行建模分析,得到了相位插值器的线性度与输入信号之间相位差、输入信号上升时间和输出节点时间常数的关系。根据分析得到的结论,提出了一种新型的应用于连续数据速率时钟数据恢复电路的相位插值器,通过在相位插值器之前插入延时可控的缓冲器,使其输入信号的上升时间可以跟踪数据速率的改变,在保证线性度的同时,降低电路的噪声敏感度和功耗。芯片采用Charterd 0.13μm低功耗1.5/3.3 V工艺流片验证,面积为0.02 mm2,数据速率3.125 Gb/s时,功耗为8.5 mW。
By modeling the phase interpolator circuit, the relationship between the linearity of the phase interpolator and the input signal, the rise time of the input signal and the time constant of the output node are obtained. According to the conclusion of the analysis, a new type of phase interpolator applied to the continuous data rate clock data recovery circuit is proposed, which can track the rise time of the input signal by inserting a delay-controllable buffer before the phase interpolator Data rate changes, while ensuring linearity, reduce the circuit noise sensitivity and power consumption. The chip uses Charterd 0.13μm low-power 1.5 / 3.3 V process flow chip verification, an area of 0.02 mm2, data rate of 3.125 Gb / s, the power consumption of 8.5 mW.