论文部分内容阅读
低电压差分信号(LVDS)是串并转换电路(SerDes)的一种主流接口技术。本文设计并实现了一种适合于8B/10B编码串并转换电路的LVDS接收器(Receiver)。本设计的指标完全兼容IEEEStd1593.3-1996标准。它支持最大0.05V至2.35V的共模电平输入范围,最小100mV的差模输入,能够在至少40英寸FR4带状线上达到1.6Gb/s的接收速率,平均功耗3mW。电路设计基于0.18μm1.8V/3.3V CMOS工艺,同时采用了3.3V器件和1.8V器件。
Low Voltage Differential Signaling (LVDS) is a mainstream interface technology for SerDes. This paper designs and implements an LVDS receiver suitable for 8B / 10B encoded serial-to-parallel conversion circuits. The design of the indicators fully compatible with IEEEStd1593.3-1996 standards. It supports a common mode level input range of up to 0.05V to 2.35V and a differential mode input of 100mV minimum, enabling a 1.6Gb / s receive rate on at least 40-inch FR4 stripline with an average power consumption of 3mW. The circuit design is based on a 0.18μm 1.8V / 3.3V CMOS process, using both a 3.3V device and a 1.8V device.