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为了降低每时钟周期的平均及峰值功耗,在两级扫描结构基础之上提出时钟屏蔽及它的改进策略。利用测试激励压缩条件和测试响应压缩条件对电路进行划分,在每个时钟周期激活子电路的方法来降低峰值。实验结果表明:采用改进策略测试的总功耗平均降低到全扫描的0.39%,峰值功耗平均降低到全扫描的16.26%,捕获阶段的峰值平均降低到全扫描的10.97%。从结果可以看出,采用多级时钟屏蔽策略进行电路测试,与传统的全扫描测试方法相比,测试功耗及其他影响扫描测试代价的参数均有明显的降低。
In order to reduce the average and peak power consumption per clock cycle, a clock mask and its improvement strategy are proposed based on the two-level scanning structure. The circuit is divided by test excitation compression conditions and test response compression conditions, and the sub-circuit is activated at each clock cycle to reduce the peak value. The experimental results show that the total power consumption of the improved strategy test is reduced to 0.39% of the full scan on average, the peak power consumption is reduced to 16.26% of the full scan on average, and the peak value of the capture phase is reduced to 10.97% of the full scan on average. As can be seen from the results, the circuit test using a multi-level clock shielding strategy has significantly reduced the test power consumption and other parameters that affect the scan test cost compared with the conventional full-scan test method.