Algorithm and Implementation of Parallel Multiplication in a Mixed Number System

来源 :Journal of Computer Science and Technology | 被引量 : 0次 | 上传用户:mrchenbx
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This paper presents a high-speed multiplication algorithm for the mixed number system of the ordinarybinary number and the symmetric redundant binary number.It is implemented with the multivalned logictheory,and 3-valued and 2-valued circuits are used.The 3-valued circuit proposed in this paper is anemitter-coupled logic circuit with high speed,simplicity and powerful functions.A 3-valued ECL thresholdgate can simultaneously produce six types of one-variable operations.The array multiplier,designed withthe algorithm and the circuits,is fast and simple,and is suitable for building LSI.It can be used in a high-speed computer just as an ordinary binary multiplier. This paper presents a high-speed multiplication algorithm for the mixed number system of the ordinary binary number and the symmetric redundant binary number. It is implemented with the multivalned logictheory, and 3-valued and 2-valued circuits are used. The 3-valued circuit proposed in this paper is anemitter-coupled logic circuit with high speed, simplicity and powerful functions. A 3-valued ECL threshold gate can simultaneously produce six types of one-variable operations. The array multiplier, designed with the algorithm and the circuits, is fast and simple, and is suitable for building LSI. It can be used in a high-speed computer just as an ordinary binary multiplier.
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