在分析基本FIR滤波器原理的基础上,设计了基于微程序的FIR滤波系统的硬件架构,并采用自顶向下的设计方法,利用硬件描述语言Verilog HDL实现了该系统,最后在Xilinx软件开发工具vivad02016.1上进行了仿真,并在Matlab软件中进行了验证.结果表明,设计的基于微程序的FIR滤波系统硬件架构可行,软件可靠,并具有阶数可扩展、可重构、可移植、占有资源少、功耗低的优点.,On the base of having analyzed the principle of the finite impulse response (FIR) filter,a hardware architecture of FIR filtering system based on microprogram was designed,and it was implemented with the hardware describe language Verilog HDL in the way of top-to-down.The proposed system was simulated on vivado2016.1,a Xilinx’s software developing tool.Then it was verified in Matlab.The results indicated that the hardware architecture was feasible,and the software was reliable.The system had the advantages of having extensible order,reconfigurability,portability,less resource occupation,and lower power.