Three-dimensional(3D) integration using through-silicon-vias (TSVs) to interconnect multilayer-stacked chips is a promising technology for reducing interconnect delay and devices size.In this paper we report on Cu plating of the through-silicon-vias (TSVs) using commercial electroplating bath with model additive (SPS, PEG, and JGB).The via, with a diameter and depth of 20 μm and 80 μm, respectively,was prepared on a Si wafer by a deep reactive ion etching (DRIE) process.Before electrodeposition, the blind holes were fully metallized with a thin sputtered copper seed layer and the wafer was immersed in the prepared electroplating bath with different additives for fully excluding bubbles.Direct current (DC) was used for plating copper.The effect of additives were measured using cathodic polarization measurement and electrochemical spectroscopy (EIS) measurement.Experimental results show that different doses of additives could affect the filling processes tremendously.