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引言MOS存储器中器件密度的提高是十分惊人的,自1970年开发1K位动态RAM以来,按照穆尔法则以每年2倍的比例向大容量化飞速发展。在这种大容量化进展的同时,最小加工尺寸的缩小化问题也是很明显的。如图1所示,1970年的最小加工尺寸为10微米,通过利用干法腐蚀技术和高精度缩小投影步进曝光方法,到1980年已达到了3微米。这样一来,在1980年就已跨入了每枚芯片上集成有10万个以上元件的MOS存储器(超大规模集成电路)时代。而且,目前2微米器件(如64K位静态随机存取存储器或256K位动态随机存取存储器)已开始大量生产,并且开始开发以下一代1微米加工技术为必要条件的元件数超过100万个的超
Introduction MOS memory devices in the density increase is very alarming, since the development of 1K bit dynamic RAM in 1970, according to Moore’s law to 2 times a year to the rapid development of large-capacity. At the same time as the progress of such a large capacity is made, the problem of minimizing the minimum processing size is also obvious. As shown in Figure 1, the minimum working size was 10 microns in 1970 and reached 3 microns by 1980 using dry-etching techniques and high-precision narrow-projection step-and-step exposures. As a result, the era of MOS memory (Very Large Scale Integrated Circuits) with more than 100,000 integrated devices per chip was tapped in 1980. Moreover, the current 2-micron devices, such as 64K-bit SRAM or 256K-bit DRAM, are already in mass production and have begun to develop the next generation of 1-micron processing technology with more than 1 million components