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基于2003ITRS、热阻经验公式、Elmore时延模型和三维集成电路互连模型,本文估算分析单栅SOI-CMOS三维集成电路的热阻θ,简介分析功耗延迟积PDP的计算结果,估算分析阈值电压的工艺容差6б。应用VC++链接Matlab,计算研究发现:主要源于垂直互连的贡献,针对90nm-45nm技术代,选取器件层m为4-8时,存在负载为N门m层的单栅SOI-CMOS与非门三维电路的热阻梯度和功耗延迟积各自的最优值。随着技术一代一代地发展,芯片热阻和阈值电压的工艺容差成为极大的工艺挑战。
Based on 2003ITRS, thermal resistance empirical formula, Elmore delay model and 3D integrated circuit interconnection model, this paper estimates and analyzes the thermal resistance θ of a single-gate SOI-CMOS three-dimensional integrated circuit, and analyzes the calculation results of the power delay product PDP, Voltage tolerance 6б. Using VC ++ link Matlab, the calculation found that: mainly due to the contribution of vertical interconnection, for 90nm-45nm technology generation, select the device layer m is 4-8, there is a load of N gate m-layer single-gate SOI-CMOS and non- Gate thermal resistance of the three-dimensional gradient and power delay product of the respective optimal value. As generations of technology have evolved, process tolerances of chip thermal resistance and threshold voltage have become great process challenges.