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给出一种流水线与阵列处理相结合的VLSI系统结构,以实现非定长码的高速实时拼接与存储。该结构不但并行处理能力强,能够在每个时钟周期内拼接一个非定长码,并且复杂度低,仅需10000门单元电路即可实现。利用ACTEL公司的现场可编程门阵列实现该功能,验证结果表明,所研制的专用芯片工作频率大于70MHz、功耗低于130mW、性能稳定可靠,具有良好的工程应用前景。
This paper presents a VLSI architecture that combines pipeline and array processing to achieve high-speed real-time splicing and storage of non-fixed-length codes. The structure not only parallel processing ability, can be spliced a non-fixed-length code in each clock cycle, and the complexity is low, only 10000 units of circuit can be realized. ACTEL company’s field programmable gate array to achieve this function, the verification results show that the developed chip operating frequency greater than 70MHz, power consumption is lower than 130mW, stable and reliable performance, with good engineering application prospects.