Delay consideration has been a majorissue in design and test of high performance digital circuits. Theassumption of input signal change occurring only when all internal nodesare stable restricts the increase of clock frequency. It is no longertrue for wave pipelining circuits. However, previous logical delaymodels are based on the assumption. In addition, the stable time of arobust delay test generally depends on the longest sensitizable pathdelay. Thus, a new delay model is desirable. This paper explores thenecessity first. Then, Boolean process to analytically describe thelogical and timing behavior of a digital circuit is reviewed. Theconcept of sensitization is redefined precisely in this paper. Based onthe new concept of sensitization, an analytical delay model isintroduced. As a result, many untestable delay faults under thelogical delay model can be tested if the output waveforms can be sampledat more time points. The longest sensitizable path length is computedfor circuit design and delay test.