We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs(having low leakage)are improved by junctionless TFETs through blending advantages of Junctionless FETs(with high on current). We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an In As channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in I_(OFF) of ~9×10~(16)A/ μm, I_(ON) of ~20 μA/ μm, I_(ON)/I_(OFF) of 2×10~(10), threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for Poly Gate/Hf O_2/In As TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and V_(DD) of 0.2 V. The characteristics of TFETs (having low leakage) are improved by junctionless TFETs through blending advantages of Junctionless FETs (with high on We further improved the characteristics, an simplifying the structure at a very low power rating using an In As channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply Simulations resulted in I_OFF of ~ 9 × 10 ~ (16) A / μm, I_ (ON) of ~ 20 μA / μm, I_On / I_OFF of 2 × 10 ~ (10), threshold voltage of 0.057 V, subthreshold slope of 7 mV / dec and DIBL of 86 mV / V for Poly Gate / Hf O 2 / In As TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and V_ (DD) of 0 .2 V.