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为降低低密度奇偶检验码译码的硬件实现复杂度,提出了一种可变步长均匀量化“和积”译码算法。该算法分为两步进行:首先,检验节点和变量节点的外信息都以相同的量化步长进行均匀量化而进行迭代译码;然后,当迭代达到预定的次数时,检验节点和变量节点的量化步长分别乘以和除以预先选定的一个参数。仿真和现场可编程门阵列实现结果表明,与未量化的标准积译码算法相比,该算法的性能损失在0.1 dB以内;与同等性能的算法相比,该算法可以降低50%的硬件规模。
In order to reduce the hardware implementation complexity of low density parity check code decoding, a variable quantization step size quantization algorithm is proposed. The algorithm is divided into two steps: First, the outer information of the test node and the variable node is uniformly quantized with the same quantization step size and iteratively decoded; then, when the iteration reaches a predetermined number of times, the check node and the variable node The quantization steps are multiplied by and divided by a preselected parameter. Simulation and field programmable gate array results show that compared with the unquantized standard product decoding algorithm, the performance loss of the algorithm is less than 0.1 dB; compared with the same performance algorithm, the algorithm can reduce the hardware size by 50% .