为了降低静态随机存储器(SRAM)的功耗,提出了一种完全采用绝热电路实现的W A SRAM(W ho le A d iabaticSRAM),W A SRAM的译码部分、存储单元、读出放大等全部采用绝热电路结构。针对W A SRAM建立了功耗分析模型。基于0.18μm 1.8 V CM O S工艺,在不同频率下针对不同存储规模的SRAM进行了功耗仿真、分析和比较。实验结果证明,W A SRAM的低功耗效果十分明显,与传统CM O S电路实现的SRAM相比,在250 MH z频率下,W A SRAM功耗降低了80%以上。 In order to reduce the power consumption of static random access memory (SRAM), WA SRAM (WAKE ADAPTIVE SRAM) which is implemented completely by adiabatic circuit is proposed. The decoding part of WA SRAM, memory cell, sense amplifier, Circuit configuration. A power analysis model is built for W A SRAM. Based on the 0.18μm 1.8 V CM O S process, power consumption simulation, analysis and comparison were performed on SRAMs with different storage scales at different frequencies. The experimental results show that the low power dissipation of W A SRAM is very clear. W A SRAM power consumption is reduced by more than 80% at 250 MHz compared to the SRAM implemented by conventional CM O S circuits.