Piezoresistive cantilevers with dimensions of 200 × 50 × 1.8μm3 have been fabricated from polycrystalline silicon using reactive ion etching (RIE) and back etching processes. Full Wheatstone bridges have been designed symmetrically on-chip, with two resistors placed on the cantilevers and two resistors on the substrate. The differential measurements of the two cantilevers can reduce the thermal shift of the signal in the system and the exteal noise in the laboratory.The characteristics of the fabricated cantilevers have been analysed by measuring the noise and the sensitivity. The measured noise spectra show that the 1/f noise is the dominant noise source at low frequencies. With the linear relation between 1/f noise and bias voltages, the Hooge factor (c) was calculated to be 0.0067. The 1/f noise was explained in terms of a lattice scattering model, which occurs in the depletion region of the grains. The displacement sensitivity of the cantilevers was calculated to be 1× 10-6nm-1 by measuring the resistance change and the vertical deflection of the cantilever. The gauge factor of the piezoresistive cantilever was calculated to be 19. At a 3V bias voltage and 1000 Hz measurement bandwidth, 1 nm of minimum detectable deflection has been obtained.