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基于新型的折叠电流镜负载PMOS差分输入级拓扑、轨至轨(Rail-to-Rail)AB类低压CMOS推挽输出级模型、低压低功耗LV/LP技术和Cadence平台的实验设计与模拟仿真,采用2μmP阱硅栅CMOS标准工艺,得到了一种具有VT=±0.7V、电源电压1.1～1.5V、静态功耗典型值330μW、75dB开环增益和945kHz单位增益带宽的LV/LP运算放大器。该器件可应用于ULSI库单元及其相关技术领域,其实践有助于CMOS低压低功耗集成电路技术的进一步发展。
Based on the novel fold-current mirror load PMOS differential input stage topology, Rail-to-Rail Class AB low-voltage CMOS push-pull output stage model, low voltage low power LV / LP technology and Cadence platform experimental design and simulation , An LV / LP operational amplifier with VT = ± 0.7V, 1.1 ~ 1.5V supply voltage, 330μW typical static power dissipation, 75dB open loop gain and 945kHz unity gain bandwidth was obtained using a 2μm P-well Si-gate CMOS standard process. . The device can be applied to the ULSI library unit and related technical fields, and its practice contributes to the further development of CMOS low-voltage and low-power integrated circuit technology.