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数字锁相环路(DPLL)是数字相干解调技术的核心。根据锁相环理论,分析了在最小等效噪声带宽、最小相位均方误差以及最短锁定时间三种意义上的参数优化设计方案,并给出了简明的、具有一定工程指导意义的结果。该结果在应用了Intel公司解调芯片STEL-2105的系统中获得了具体应用。
Digital Phase-Locked Loop (DPLL) is the heart of digital coherent demodulation technology. According to the theory of phase-locked loop, the optimal design scheme of parameters in the three sense of minimum equivalent noise bandwidth, mean square error of minimum phase and shortest lock time is analyzed, and concise results with some engineering significance are given. The results obtained in the application of the Intel company STEL-2105 demodulator chip system was obtained.