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日立制作所和TI公司共同开发64MDRAM。工艺采用0．35PmCMOS，芯片面积为228mm’，确定i线的微细加工技术，作为缺陷弥补技术，由于设计成新型高效率补救电路，从制作初期开始就实现稳定的高成品率。电源电压实现3．3V土0．3V的低电压化，也可用于LVTTL（低压TTL）的接口中。另
Hitachi and TI jointly develop 64MDRAM. 0.35Pm CMOS process technology, the chip area of 228mm ’, i line to determine the fine processing technology, as a defect remedy technology, due to the design of a new type of high efficiency remediation circuit, from the beginning of production to achieve stable high yield. 3.3V power supply voltage to achieve the 0.3V low voltage of soil, can also be used LVTTL (low voltage TTL) interface. another