基于FPGA的半硬回收数据采集存储系统设计

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文章介绍了基于FPGA的半硬回收数据采集存储系统的多片A/D数据编码技术、有限硬件资源下的大容量Flash读写技术、USB接口设计.利用VHDL语言和QuartusⅡ7.1软件完成了系统设计及软件仿真.实验表明:所设计的系统实现了16通道10 kHz的数据采样和存储,与计算机接口数据传输速率达8 Mbit/s,系统运行稳定可靠.
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