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为了减小电路延迟,提出基于忆阻器蕴含门的逻辑电路综合多阶段进化算法(IMP-ELS),求得在工作忆阻器数目取不同值的条件下的脉冲数优化电路.将问题建模为等式约束下的最小化问题,当约束违反降低到一定程度时,通过判别当前最优解与待求函数真值表符合的条件,计算与、或、异或三种余项函数之一,将其作为新的待求函数,启动新一轮进化,从而保证得到电路的可行解;设计蕴含门逻辑电路编码及初始化方法,减少随机初始化种群中的非法解和冗余门.对2~11bit标准逻辑函数测试结果表明:当工作忆阻器数目由2增大到3时,该算法对82%的测试函数平均脉冲数降低了28%.
In order to reduce the circuit delay, an IMP-ELS algorithm based on memristor implicated gate logic is proposed to obtain the pulse number optimization circuit with different values of working memristor. When the constraint violation is reduced to a certain degree, the model is defined as the minimization problem under equality constraints. By determining the conditions that the current optimal solution meets the truth table of the function to be sought, the sum of the three kinds of residual functions First, as a new function to be solved, a new round of evolution is started, so as to ensure that the feasible solution of the circuit is obtained. The design contains the coding and initialization method of the gate logic circuit to reduce the illegal initialization and redundant gates in the random initialized population. The ~ 11bit standard logic function test results show that when the number of working memristor is increased from 2 to 3, the average number of pulses of the 82% test function is reduced by 28%.