To obtain a low-power and compact implementation of the advanced encryption standard (AES) S-box, an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper. In the presented S-box, some improvements were made as follows. (1) Level-sensitive latches were inserted in data path to block the propagation of the dynamic hazards, which lowered the power of data path circuit. (2) Operations of latches were controlled by latch controllers based on presented asynchronous sequence element: LC-element, which utilized static asymmetric C-element to construct a simple and power-efficient circuit structure. (3) Implementation of the data path circuit was a semi-custom standard-cell circuit on 0.25μm complementary mental oxide semiconductor (CMOS) process; and the full-custom design methodology was adopted in the handshake circuit design. Experimental results show that the resulting circuit achieves nearly 46% improvement with moderate area penalty (11.7%) compared with the related composite field S-box in power performance. The presented S-box circuit can be a hardware intelligent property (IP) embedded in the targeted systems such as wireless sensor networks (WSN), smartcards and radio frequency identification (RFID).