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本文设计了适用于SOC(System On Chip)的快速乘法器内核。通过增加一位符号位,可以支持24×24无符号和有符号乘法。在乘法器的设计中,采用了改进的Booth算法来减少部分积的数目,用压缩的Wallace Tree结构将产生的部分积相加以减少关键路径的延时。该电路通过Hspice仿真最大延迟达到9.32ns,从而获得较高的速度和性能。
This article designed a fast multiplier core for SOC (System On Chip). By adding a sign bit, can support 24 × 24 unsigned and signed multiplication. In the design of the multiplier, an improved Booth algorithm is used to reduce the number of partial products, and the partial products generated by the compressed Wallace Tree are added to reduce the critical path delay. The circuit achieves a 9.32 ns maximum latency through Hspice emulation, resulting in higher speed and performance.