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本文描述了一种可用于 CDMA2 0 0 0通信系统的通用高速维特比译码器基于 FPGA的设计与实现。该维特比译码器具有通用性和高速性 ,它支持可变码率、可变帧长的译码。同时它采用四个 ACS并行运算的结构 ,译码速度可高达 5 88kbit/s,可以方便地运用于第三代移动通信系统和其它许多系统
This paper describes a FPGA-based design and implementation of a general purpose high speed Viterbi decoder that can be used in a CDMA2000 system. The Viterbi decoder has the versatility and high speed, it supports variable bit rate, variable frame length decoding. At the same time it uses four ACS parallel computing structure, decoding speeds up to 5 88kbit / s, can be easily used in third-generation mobile communications systems and many other systems