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本文阐述了用于GaAs单片集成的Ti—Au系肖特基势垒的有关特性。指出了实现既要有1微米栅长的几何图形,又要有良好电学特性的肖特基势垒的制作条件。采用栅区深腐蚀法和盐酸浸泡法,改善了肖特基势垒特性。针对高温下结退化问题,测量了Ti—Au势垒的正向特性随温度变化的数据,分析了势垒劣化的机理。提出了减小势垒退化应采取的制作方法。
This article describes the relevant characteristics of the Ti-Au based Schottky barrier for GaAs monolithic integration. The fabrication conditions for a Schottky barrier that achieves both the geometry of a 1 micron gate length and good electrical characteristics are also pointed out. The use of gate deep etching and hydrochloric acid immersion method to improve the Schottky barrier characteristics. Aiming at the problem of junction degeneration at high temperature, the mechanism of the barrier degradation was analyzed. The data of the forward characteristic of Ti-Au barrier with temperature were measured. Proposed to reduce the barrier degradation should take the production method.