论文部分内容阅读
硬件系统的规模越来越大,复杂度越来越来高,对其进行测试也越来越困难,JTAG边界扫描技术较好地解决了传统测试的不足,边界扫描测试是一种新型的VLSI电路测试及可测试性设计方法。JTAG是符合IEEE规范的测试技术,JTAG的设计实现了测试复杂度的降低,适合进行大规模集成电路的测试。论述边界扫描技术的结构特征及软核设计方法的同时,分析了JTAG电路中数据传输的路径及电路对速度的影响,并以采样指令为例进行了功能仿真。
The scale of the hardware system is getting bigger and bigger, the complexity is more and more high, it is more and more difficult to test it. The JTAG boundary scan technology solves the problem of the traditional test, the boundary scan test is a new VLSI Circuit testing and testability design. JTAG is in line with the IEEE standard test technology, JTAG design to achieve a reduction of test complexity, suitable for large-scale integrated circuit testing. The structure of the boundary-scan technique and the design method of the soft-core are discussed. At the same time, the path of the data transmission in the JTAG circuit and the influence of the circuit on the speed are analyzed. The function of the sampling instruction is simulated.