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针对多元低密度奇偶校验码(LDPC)译码器的资源消耗过大问题,设计了一种采用扩展最小和算法的低资源需求的多元LDPC译码器.采用以块为单位对信息进行迭代更新和Flooding传递调度策略的结构.为降低译码器的存储资源和逻辑资源,首先减小传递信息的深度,将变量节点更新和校验节点更新进行联合设计.同时,利用迭代时间差对变量节点更新和校验节点信息所需的资源进行复用.在具体实现中,对一个GF(64)域上码长为1044bit的非规则多元LDPC码,采用Xilinx公司XC4VLX60的现场可编程逻辑门阵列(FPGA)芯片设计了译码器.与现有文献相比,所提出的译码器结构可节约54%的存储资源和逻辑资源,且提高了译码速度和吞吐量.
In order to solve the problem of excessive resource consumption of LDPC decoder, a multi-LDPC decoder with low resource requirement of extended minimum and algorithm is designed, and the information is iterated on a block-by-block basis Update and Flooding scheduling strategy.In order to reduce the storage resources and logic resources of the decoder, firstly, the depth of information transfer is reduced, the variable nodes are updated and the check nodes are updated for joint design.At the same time, Update and check the node information required for multiplexing.In a specific implementation, an irregular multi-LDPC code with a code length of 1044bit on a GF (64) domain is implemented by Xilinx XC4VLX60 field programmable gate array FPGA) chip design of the decoder.Compared with the existing literature, the proposed decoder structure can save 54% of the storage resources and logic resources, and improve the decoding speed and throughput.