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基于扩展的真单相时钟(E-TSPC)技术,设计了一款用于10 GHz扩频时钟发生器(SSCG)的分频比范围为32~63的多模分频器(MMD)。在设计中,基于D触发器的2/3分频器采用了动态E-TSPC技术,这不仅降低了功耗和芯片面积,而且改善了最高工作频率。MMD由5级2/3分频器级联而成,由5 bit数字码控制。详细介绍和讨论了2/3分频器和MMD的工作原理和优势。MMD是SSCG的一部分,采用55 nm CMOS工艺进行了流片,芯片面积为35μm×10μm,电源电压为1.2 V,最高工作频率为10 GHz,此时功耗为1.56 m W。
Based on the extended True Single-Phase Clock (E-TSPC) technology, a multi-mode divider (MMD) with a 32 to 63 division ratio for a 10 GHz spread spectrum clock generator (SSCG) was designed. In the design, the D flip-flop based 2/3 divider uses dynamic E-TSPC technology, which not only reduces power consumption and chip area, but also improves the maximum operating frequency. The MMD consists of 5 stages of 2/3 dividers cascaded and controlled by a 5 bit digital code. Described in detail and discussed 2/3 frequency divider and MMD working principle and advantages. The MMD, part of the SSCG, is streamed in a 55 nm CMOS process with a 35μm × 10μm chip area, a 1.2V supply voltage and a maximum operating frequency of 10GHz, consuming 1.56mW at this time.