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就如何同时实现多元逻辑电路中线性“与或”门的高速和高均匀性进行 了理论分析和实验验证。理论分析给出了平均延迟时间和均匀性的函数表达 式；指出在影响电路速度和均匀性的诸多因素中，复合晶体管的发射结面积 是一个关键因素，并依此进行了样品电路的优化设计和工艺制造。测试结果 表明，单门平均延迟时间为 ０．２２ ｎｓ，功耗延迟积为 ０．５５ ｐＪ．在输入一致条 件下（０～４ Ｖ），各单门电路之间输出不均匀性误差小于等于４ ｍＶ．
The theoretical analysis and experimental verification on how to realize the high-speed and high-uniformity of the linear AND gate in the multiple logic circuits are carried out at the same time. The theoretical analysis shows the function expression of average delay time and uniformity. It is pointed out that the emitter area of the compound transistor is a key factor in many factors affecting circuit speed and uniformity, and the optimal design of the sample circuit And craft manufacturing. The test results show that the average delay time of a single gate is 0.22 ns, and the power delay product is 0.55 pJ. Under the same input conditions (0 ~ 4 V), the output inhomogeneity error between each single circuit is less than or equal to 4 mV.