提出了一种两相非交叠时钟双SHA结构的12位50 MSPS流水线逐次逼近A/D转换器。电路在OrCAD/PSpice10.5平台上进行仿真和测试。结果表明,该A/D转换器最高采样速率为50 MSPS。在0.05 MHz和0.10 MHz信号输入下,有效位数分别为11.4位和10.7位;在2.00 MHz和4.00 MHz下,有效位数分别为7.4位和7.1位。给出了A/D转换器的总体结构和模块结构,以及测试波形和动态测试结果。 A 12-bit 50 MSPS pipeline sequential approximation A / D converter with two-phase non-overlapping clock double-SHA structure is proposed. The circuit is simulated and tested on the OrCAD / PSpice10.5 platform. The results show that the A / D converter maximum sampling rate of 50 MSPS. The valid digits are 11.4 bits and 10.7 bits for the 0.05 MHz and 0.10 MHz signals, respectively; and at 2.00 MHz and 4.00 MHz, the effective digits are 7.4 and 7.1 respectively. The overall structure and module structure of the A / D converter, the test waveform and the dynamic test results are given.