SYNCHRONOUS DERIVED CLOCK AND SYNTHESIS OF LOW POWER SEQUENTIAL CIRCUITS

来源 :Journal of Electronics(China) | 被引量 : 0次 | 上传用户:wufato
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Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew.
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