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A new low-power,area efficiency all-digital delay-locked loop(ADDLL)circuit is proposed for DDR3application.The ADDLL can process the input clock frequency ranging from 333 MHz to 800 MHz(DDR3-667/800/1066/1600)by using Phase Detector(PD),Delay Control Delay Line(DCDL),Digital Loop Filter Controller(DLFC)and Delay Generator(DG).To achieve 1.6 Gb/s/pin operation,a novel DCDL scheme is employed.The DCDL has a small delay with a shunt capacitor based digitally controlled delay element.A splitcontrol thermometer-code generator generates the control voltages used to set a current in the current-starved inverters.The testchip fabricated with a 40-nm CMOS process gives the ADDLL data rate of 667 Mbps–1.6 Gbps.Experimental results that show the power consumption is 1.87 m W at 1.1 V with active area is 0.0137mm2.
A new low-power, area efficiency all-digital delay-locked loop (ADDLL) circuit is proposed for DDR3 application. The ADDLL can process the input clock frequency ranging from 333 MHz to 800 MHz (DDR3-667 / 800 / 1066/1600) by using Phase Detector (PD), Delay Control Delay Line (DCDL), Digital Loop Filter Controller (DLFC) and Delay Generator (DG) .To achieve 1.6 Gb / s / pin operation, a novel DCDL scheme is employed. DCDL has a small delay with a shunt capacitor based digitally controlled delay element. A splitcontrol thermometer-code generator generates the control voltages used to set a current in the current-starved inverters. the testchip fabricated with a 40-nm CMOS process gives the ADDLL data rate of 667 Mbps-1.6 Gbps. Experimental results that show the power consumption is 1.87 mW at 1.1 V with active area is 0.0137 mm2.