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本文报导了沟道长度为5μm的高速硅栅CMOS电路,门电路平均延迟时间为10nS,触发器最高工作频率为30—40MHz。文中给出了CAD模拟计算结果和工艺措施,对高速CMOS电路作了初步研究。
This paper reports a high-speed silicon gate CMOS circuit with a channel length of 5μm. The average delay time of the gate is 10nS and the maximum operating frequency of the flip-flop is 30-40MHz. The paper gives the CAD simulation results and process measures, made a preliminary study of high-speed CMOS circuits.