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在以SDRAM为主的存储系统中,SDRAM的换行访问产生了大量的功耗开销,减少换行次数可以降低存储系统功耗。本文提出了引入片上存储器来降低SDRAM换行次数的低功耗设计策略。该策略首先对指令执行流进行分析,并统计出在对堆栈和全局变量的访问时产生了频繁换行;然后将堆栈放入片上堆栈存储器;同时借助有芯片面积约束的贪婪算法确定了片上数据存储器的大小和所存放的全局变量。实验结果表明,引入较小的片上存储器就使得换行次数大大降低,功耗显著下降,减少换行访问的功耗平均下降了24%。
In the SDRAM-based storage system, SDRAM wrapper access generated a lot of power consumption overhead, reducing the number of line breaks can reduce the storage system power consumption. This paper proposes a low-power design strategy that introduces on-chip memory to reduce the number of SDRAM line-feeds. The strategy first analyzes the flow of instruction execution and statistically generates frequent line breaks when accessing stacks and global variables. The stack is then placed on-chip stack memory. The on-chip data memory is also determined by the greedy algorithm with chip area constraints The size and the stored global variables. Experimental results show that the introduction of smaller on-chip memory greatly reduces the number of line breaks and power consumption, and reduces the average power consumption for line feed access by 24%.