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根据产品目录,7CS23型J—K触发器的电路图如图1所示。电路的上半部分是由两个TTL门电路构成的基本R—S触发器,下半部分是保证电路可靠翻转的导引电路。电路逻辑图示于图2。其中CP_1和CP_2作为计数输入端;R_(D1)、R(D2)是触发器的直接置“0”端;S_(D1);、S_(D2)。是触发器的直接置“1”端;K_1、K_2和J_1、J_2是数据输入端。许多资料都谈到了TTL集成电路J—K触发器的逻辑功能。在R_D端输入负脉冲,J—K触发器就被置“0”,
According to product catalog, 7CS23 type J-K flip-flop circuit diagram shown in Figure 1. The top half of the circuit is a basic R-S flip-flop consisting of two TTL gates, and the bottom half is the pilot circuit that ensures a reliable flip of the circuit. The circuit diagram is shown in Figure 2. Which CP_1 and CP_2 as the count input; R_ (D1), R (D2) is the flip-flop directly set the “0” side; S_ (D1) ;, S_ (D2). Is the flip-flop directly set “1” end; K_1, K_2 and J_1, J_2 is the data input. Many sources talk about the logic functions of the TTL J-K flip-flop. Input a negative pulse on the R_D side, J-K flip-flop is set to “0”