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The paper proposes a novel ATPG (Automatic Test Patt Generation) methodbased on RTL (Register Transfer Level) behavioral descriptions in HDL (Hardware DescriptionLanguage). The method is simulation-based. Firstly, it abstracts RTL behavioral descriptionsto Process Controlling Trees (PCT) and Data Dependency Graphs (DDG), which are used forbehavioral simulation and data tracing. Transfer faults are extracted from DDG edges, whichcompose a fault set needed for test generation. Then, simulation begins without specifying inputsin advance, and a request-echo strategy is used to fix some uncertain inputs if necessary. Finally,when the simulation ends, the partially fixed input sequence is the generated test sequence. Theproposed request-echo strategy greatly reduces unnecessary backtracking, and always tries to coveruncovered transfer faults. Therefore, the proposed method is very efficient, and generates tests withgood quality. Experimental results demonstrate that the proposed method is better than ARTISTin three aspects: (1) the CPU time is shorter by three orders of magnitude; (2) the test length isshorter by 52%; and (3) the fault coverage is higher by 0.89%.