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为了应用FPGA中内嵌的数字时钟管理(DCM)模块建立可靠的系统时钟.首先对DCM的工作原理进行分析,然后根据DCM的工作原理给出了一种DCM动态重配置的设计方法.DCM动态重配置设计是利用一个常有的时钟对DCM的工作状态标识进行监测,当DCM由于输入时钟的瞬时抖动或突然变化而失锁后,自动产生一个脉冲将DCM复位,使其重新锁定并恢复正常工作.实验结果表明:DCM动态重配置设计中,恢复时间的设计是DCM重配置成功的关键,在xc2vp40芯片中,当恢复时间大于10ms时,DCM可以被复位并重新配置成功.“,”In order to use the digital clock manage (DCM) module embedded in FPGA to establish reliable system clock. First of all, make a analyse to principle of DCM,and then ,According to the principle of DCM offered a DCM dynamic re-configuration design. The DCM dynamic re-configuration design is using a always worked clock to monitor the output state mark of DCM, once the DCM is found working abnormally because of the disturbance or change on the input clock,generate a pluse to get the DCM re-locked and work again. Experimental results show that the key of success of re-configuration is the design of the resume time.In the chip of xc2vp40, once the resmue time beyond 10 ms. The DCM can be reset and re-configuration successfully.