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设计了一种应用于802.11a的64点FFT/IFFT处理器.采用单蝶形4路并行结构,提出了4路并行无冲突地址产生方法,有效地提高了吞吐率,完成64点FFT/IFFT运算只需63个时钟周期.提出的RAM双乒乓结构实现了对输入和输出均为连续数据流的缓存处理.不仅能实现64点FFT和IFFT,而且位宽可以根据系统任意配置.为了提高数据运算的精度,设计采用了块浮点算法,实现了精度与资源的折中.16位位宽时,在HJTC 0.18μmCMOS工艺下综合,内核面积为:0.626 7 mm2,芯片面积为:1.35 mm×1.27 mm,最高工作频率可达300 MHz,功耗为126.17 mW.
A 64-point FFT / IFFT processor for 802.11a is designed.Using a single butterfly 4-way parallel architecture, a 4-way parallel collision-free address generation method is proposed, which effectively improves the throughput and completes the 64-point FFT / IFFT Computing only 63 clock cycles.The proposed RAM dual-ping-pong structure to achieve a continuous stream of input and output data cache processing can not only achieve 64-point FFT and IFFT, and the bit width can be arbitrarily configured according to the system.In order to improve the data The accuracy of the calculation, the design uses a block floating-point algorithm to achieve a compromise between accuracy and resources .16-bit wide, integrated in the HJTC 0.18μmCMOS process, the core area of 0.626 7 mm2, the chip area of 1.35 mm × 1.27 mm with a maximum operating frequency of 300 MHz and a power consumption of 126.17 mW.