A low-power multi-phase clock 20Gb/s1:4 Demultiplexer(DEMUX) without inductors is designed in 0.18μm Complementary metal oxide semiconductor(CMOS) process. The 1:4 DEMUX includes two 1:2DEMUX cells, one 1/2 frequency divider cell, some data and clock buffers. A dynamic CMOS logic latch is used in the 1:2 DEMUX cell and a single clock dynamic-loading latch is used in the 1/2 frequency divider cell. These two kinds of logical structures not only reduce power dissipation and area, but also have an output rail-to-rail level. The rail-to-rail level can offer high noise margin and implement seamless connection without logic level conversion in system integration. The test results show that when the data rate of the input pseudorandom is 20Gb/s and the sequence length is 231-1, this 1:4 DEMUX can work well at a supply voltage of 2V. The output swing is 450 m V with external 50 Ohm load and the die size is 0.475×0.475mm2. The chip power dissipation is 86 m W, when four pads connect with a four-channel oscillograph. The 1: 4 DEMUX includes two 1: 2DEMUX cells, one 1/2 frequency (CMOS) process. The low-power multi-phase clock 20 Gb / s 1: 4 Demultiplexer (DEMUX) without inductors is designed in 0.18 μm Complementary Metal Oxide Semiconductor divider cell, some data and clock buffers. A dynamic CMOS logic latch is used in the 1: 2 DEMUX cell and a single clock dynamic-loading latch is used in the 1/2 frequency divider cell. reduce power dissipation and area, but also have an output rail-to-rail level. The rail-to-rail level can offer high noise margin and implement seamless connection without logic level conversion in system integration. The test results show that when the data rate of the input pseudorandom is 20Gb / s and the sequence length is 231-1, this 1: 4 DEMUX can work well at a supply voltage of 2V. The output swing is 450 m V with external 50 Ohm load and the die size is 0.475 × 0.475mm2. The chip power dissipation is 86 m W, when four pads connect with a fo ur-channel oscillograph.