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本文通过外延区为均匀掺杂的ＶＤＭＯＳ穿通击穿条件和外延区比导通电阻Ｒｏｎ的理论分析，首次得到了Ｒｏｎ随外延区参数、击穿电压变化的简捷普遍关系式．在此基础上提出了ＶＤＭＯＳ为均匀掺杂外延区时的优化设计理论：对于各种高压ＶＤＭＯＳ，只要外延区厚度取为同衬底浓度下突变结击穿时耗尽层宽度的最佳分割长度，即穿通因数Ｆ的倒数η为０７５ 时，就可保证外延区Ｒｏｎ为最小．凭借此理论，本文首次推出了ＶＤＭＯＳ外延区优化设计的严格理论公式，纠正了一些文献引用经验关系或突变结关系导出的设计公式的不准确性及错误结论．这些理论结果可直接作为功率ＭＯＳ等非电导调制器件的设计准则．
In this paper, we first obtain the simple universal relation of the parameters of Ron along with the epitaxial region and the breakdown voltage through the theoretical analysis that the epitaxial region is uniformly doped VDMOS through breakdown condition and the epitaxial region to on-resistance Ron. On this basis, the optimal design theory of VDMOS for uniformly doped epitaxial region is proposed. For all kinds of high-voltage VDMOS, as long as the thickness of the epitaxial region is taken as the best depletion layer width at the same substrate concentration The length of the segment, ie, the reciprocal η of the punch-through factor F, is 0.75, so as to ensure that the epitaxial region Ron is the smallest. By virtue of this theory, this dissertation first introduced the strict theoretical formula of VDMOS extension design, and corrected the inaccuracy and wrong conclusion of some design formulas derived from empirical or catastrophic junction. These theoretical results can be directly used as power MOS and other non-conductive modulation device design criteria.