论文部分内容阅读
时序逻辑电路的一般设计是数字电路设计的重要方面,在设计过程中的状态化简是设计结果是否最佳的关键环节。文章就状态等效的基本概念、状态化简的步骤作了详细的介绍。
The general design of sequential logic circuits is an important aspect of digital circuit design. The simplification of the states in the design process is the key to whether the design result is the best. The paper introduces the basic concept of state equivalence and the steps of state simplification.