The shrinking silicon feature size causes the continuous increment of the aging effect due to the negative bias temperature instability(NBTI), which becomes a potential stopper for IC development. As the basis of circuit-level aging protection, an efficient aging critical-gate identification method is crucially required to select a set of gates for protection to guarantee the normal lifetime of the circuits. The existing critical-gate identification methods always depend on a critical path set which contains so many paths that its generation procedure requires undesirable CPU runtime; furthermore, these methods can achieve a better solution with taking account of the topological connection. This paper proposes a time-efficient critical gates identification method with topological connection analysis, which chooses a small set of critical gates. Experiments over many circuits of ITC99 and ISCAS benchmark demonstrate that, to guarantee the normal lifetime(e.g., 10 years) of each circuit, our method achieves a 3.97 x speedup and saves as much as 27.21% area overhead compared with the existing methods. The shrinking silicon feature size causes the continuous increment of the aging effect due to the negative bias temperature instability (NBTI), which becomes a potential stopper for IC development. As the basis of circuit-level aging protection, an efficient aging critical-gate identification method is crucially required to select a set of gates for protection to guarantee the normal lifetime of the circuits. The existing critical-gate identification methods always depend on a critical path set which contains so many paths that its generation procedure requires only CPU runtime; , this methods can achieve a better solution with taking account of the topological connection. This paper proposes a time-efficient critical gates identification method with topological connection analysis, which chooses a small set of critical gates. Experiments over many circuits of ITC99 and ISCAS benchmark demonstrate that, to guarantee the normal lifetime (eg, 10 years) of each circuit, our method achieves a 3.97 x speedup and saves as much as 27.21% area overhead compared with the existing methods.