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随着深亚微米工艺技术条件的应用和芯片工作频率的不断提高 ,芯片互连线越来越成为一个限制芯片性能提高和集成度提高的关键因素 :互连线延迟正逐渐超过器件延迟 ;互连线上信号传输时由于串扰引起的信号完整性问题已成为深亚微米集成电路设计所面临的一个关键问题。文中分析了芯片中器件和互连线的延迟趋势 ,模拟分析了 0 .1 8μm CMOS工艺条件下的信号完整性问题。
With the application of deep sub-micron technology conditions and increasing chip operating frequency, chip interconnects are increasingly becoming a key factor that limits chip performance and increase integration: the interconnect delay is gradually surpassing the device delay; Signal integrity problems due to crosstalk during on-line signal transmission have become a key issue for deep submicron integrated circuit designs. In this paper, the delay trend of the devices and interconnects in the chip is analyzed, and the signal integrity problem under the condition of 0.18μm CMOS technology is simulated and analyzed.