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SoC已经成为嵌入式系统必不可少的解决方案。验证如此复杂的嵌入式SoC是非常困难的,系统设计需要新的验证技术更快更好地完成系统功能验证任务。通过比较当前3种主要的嵌入式系统验证技术:软件仿真技术、硬件模拟技术、硬/软件协同验证仿真技术,介绍基于指令集仿真器和FPGA相结合的、面向IP核复用的混合级硬/软件协同验证环境,并提出混合级协同验证总线功能模块的构成。该技术不仅可以提高设计的可信性和验证速度,而且能够继承当前大多数硬件模拟验证方法。
SoC has become an indispensable solution for embedded systems. To verify such a complex embedded SoC is very difficult, the system design requires new verification technology to complete the system functional verification tasks faster and better. By comparing the current three kinds of main embedded system verification technologies: software simulation technology, hardware simulation technology and hardware / software co-verification simulation technology, this paper introduces a mixed-level hardware based on combination of instruction set simulator and FPGA for IP core multiplexing / Software collaborative verification environment, and proposed hybrid-level collaborative verification bus functional modules. This technology can not only improve the credibility of the design and verification speed, but also to inherit most of the current hardware simulation verification method.