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时间触发协议是TTA架构必需的通信协议,用于在要求高可靠性的分布式容错实时系统中电子模块之间的互连。目前作为时间触发通信系统重要组成部分的时间触发控制器主要是采用处理器来实现协议的处理,协议开销比较大。基于FPGA的时间触发协议控制器的设计,采用了具有较好同步能力的编码方式和合理的帧格式,在建立全局时间基准的基础上优化了协议处理状态机,利用FPGA的并行处理能力,降低了协议开销,增加了总线的效率,同时也提高了时钟同步精度和容错能力。仿真结果表明,基于FPGA的时间触发协议控制器具有较好的性能。
The time-triggered protocol is a necessary communication protocol for the TTA architecture for interconnecting electronic modules in a distributed, fault-tolerant real-time system that requires high reliability. At present, the time-triggered controller, which is an important part of the time triggered communication system, mainly adopts a processor to implement the protocol processing, and the protocol overhead is relatively large. FPGA-based time-triggered protocol controller design, using a better synchronization coding and reasonable frame format, based on the establishment of a global time base to optimize the protocol processing state machine, the use of FPGA parallel processing capabilities to reduce The protocol overhead, increasing the bus efficiency, but also improve the clock synchronization accuracy and fault tolerance. Simulation results show that FPGA-based time triggered protocol controller has better performance.