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本文提出一种新的 PLA 折叠方法叫作互补对串联折叠法(Comple-mentary Pair Series Folding——CPSF)。该种方法特别适用那些输入项多为互补对(x 和(?))而输出项并不甚多的 PLA。在一个互补对串联折叠的 PLA 中,如果每个互补对(列)都能被折叠,它的“与平面”面积可减少40%。用该种方法折叠的 PLA 的开关速度比未折叠的要高。本文设计了一个 MOS 功率反相门作为 x 与(?)间的驱动器。并用 SPICE 对它进行了模拟。本文还给出了 CPSF 的算法并讨论了与它相关的图论问题。
In this paper, a new method of PLA folding is called Complementary pair Series Folding (CPSF). This method is especially suitable for PLA where the input is mostly complementary (x and (?)) And the output is not very large. In a complementary pair of tandemly folded PLAs, the “and planar” area can be reduced by 40% if each complementary pair (column) can be folded. PLA folded in this way is faster than unfolded. In this paper, a MOS power inverted gate is designed as a driver between x and (?). And simulate it with SPICE. This paper also gives the algorithm of CPSF and discusses the graph theory related to it.