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定时恢复是全数字接收机中的核心部分之一,其处理速度制约了整个接收机的最高处理速度。在传统Gardner定时环路的实现基础上,提出了一种适用于高速数字接收机中定时同步环路的并行控制方式。它通过采用并行处理的方法,为符号同步环路中的内插滤波器提供插值相位来实现插值功能,并且降低了定时同步环路的工作时钟。MATLAB仿真证明这种插值滤波控制器在降低定时同步环路工作时钟频率的同时,定时恢复性能并未受到影响。
Timing recovery is one of the core parts of all-digital receiver, the processing speed of which limits the maximum processing speed of the entire receiver. Based on the realization of the traditional Gardner timing loop, a parallel control scheme suitable for the timing synchronization loop in high speed digital receiver is proposed. It achieves the interpolation function by using the parallel processing method to provide the interpolation phase for the interpolation filter in the symbol synchronization loop and reduces the working clock of the timing synchronization loop. MATLAB simulation proves that the interpolation filter controller reduces the frequency of the working clock of the timing synchronization loop and the timing recovery performance is not affected at the same time.