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为了获得高耐压、低导通电阻的横向双扩散MOSFET(LDMOS)器件,综合利用高介电常数(高k)薄膜技术和场板技术,设计出一种漂移区表面采用“高k薄膜+氧化层+场板”结构的功率器件,有效降低了PN结弯角高电场和场板边缘峰值电场。使用器件仿真工具MEDICI进行验证,并分析高k薄膜厚度、氧化层厚度、高k薄膜相对介电常数以及栅场板长度对器件性能的影响,最终实现了耐压达到820V、比导通电阻降至13.24Ω.mm2且性能稳定的LDMOS器件。
In order to obtain a high breakdown voltage, low on-resistance lateral double-diffused MOSFET (LDMOS) device, the combination of high dielectric constant (high-k) thin film technology and field-plate technology is used to design a drift region surface using “ + Oxide + field plate ”structure of the power device, effectively reducing the PN junction angle of the high electric field and the edge of the field plate peak electric field. The device simulation tool MEDICI was used to verify and analyze the influence of the high-k film thickness, the oxide thickness, the relative dielectric constant of high-k film and the length of the gate field plate on the device performance. Finally, the breakdown voltage reached 820V, To 13.24Ω.mm2 and stable LDMOS devices.