提出了1种可以抵抗双节点翻转的锁存器.该锁存器的反馈回路由保护门、延迟单元以及3选2多数表决器构成.保护门的输出送入表决器进行表决,表决之后的值经过延迟单元之后再反馈给保护门.分析和仿真表明,当单粒子翻转的维持时间小于500 ps时,这种结构不仅可以抵抗双节点翻转,还能抵抗部分3节点翻转以及输入端口的单粒子瞬态.在0.18μm CMOS工艺下,锁存器的面积为186.12μm2,在时钟转换时间和数据转换时间都为0.008~1.5 ns时,锁存器的建立时间为1.165 63~1.328 71 ns.此外,用这种锁存器实现了1套标准单元库,并在此基础上设计了1种序列检测器电路,其面积和动态功耗分别是用3模冗余方法的83.06%和41.99%,是用5模冗余方法的53.99%和25.19%. A kind of latch that can resist the reversal of two nodes is proposed.The feedback loop of the latch is composed of a protection gate, a delay unit and a majority voter 3 to 3. The output of the protection gate is put into a voter for voting and voting The value is fed back to the protection gate after the delay cell.The analysis and simulation show that this structure not only can resist the double node inversion but also can resist part of the 3-node inversion and the input port single when the maintenance time of the single-particle inversion is less than 500 ps Particle Transient: With a 0.18μm CMOS process, the latch area is 186.12μm2 and the latch settling time is 1.165 63 ~ 1.328 71 ns with a clock conversion time and data conversion time of 0.008 ~ 1.5 ns. In addition, a set of standard cell library is realized with this kind of latch, and on the basis of this, a kind of sequence detector circuit is designed, the area and the dynamic power consumption are respectively 83.06% and 41.99% of the 3-mode redundancy method, , Using 53.99% and 25.19% of the 5-mode redundancy method.