VDSM工艺下,芯片的高速、高集成度趋势使电磁耦合作用不容忽略;而电感效应的引入使VLSI设计和验证变得复杂。本文阐述了VLSI片上互连线电感提取技术现状及发展方向,对各类提取方法作了扼要比较;同时探讨了互连分析中包含电感效应时存在的部分问题和解决办法,以期作为提高VLSI设计、分析和验证效率的有效向导。 VDSM process, the chip’s high-speed, high integration trend so that electromagnetic coupling can not be ignored; and the introduction of inductive effects VLSI design and verification become more complicated. In this paper, the current situation and development direction of the VLSI on-chip interconnect line inductance extraction technology are described, and various extraction methods are briefly compared. At the same time, some problems and solutions in the inclusion of the inductance effect in the interconnect analysis are discussed in the hope of improving the VLSI design , An effective guide to analyze and verify efficiency.