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A limiting amplifier IC implemented in 65 nm CMOS technology and intended for high-speed optical fiber communications is described in this paper.The inductorless limiting amplifier incorporates5-stage 8 dB gain limiting cells with active feedback and negative Miller capacitance,a high speed output buffer with novel third order active feedback,and a high speed full-wave rectifier.The receiver signal strength indictor(RSSI) can detect input signal power with 33 dB dynamic range,and the limiting amplifier features a programmable loss of signal(LOS) indication with external resistor.The sensitivity of the limiting amplifier is 5.5mV at BER = 10 ~(-12) and the layout area is only 0.53 ×0.72 mm because of no passive inductor.The total gain is over 41 dB,and bandwidth exceeds12 GHz with 56 mW power dissipation.
A limiting amplifier IC implemented in 65 nm CMOS technology and intended for high-speed optical fiber communications is described in this paper. The inductorless limiting amplifier incorporates5-stage 8 dB gain limiting cells with active feedback and negative Miller capacitance, a high speed output buffer with novel third order active feedback, and a high speed full-wave rectifier. receiver receiver signal strength indictor (RSSI) can detect input signal power with 33 dB dynamic range, and limiting amplifier features a programmable loss of signal (LOS) indication with external resistor. The sensitivity of the limiting amplifier is 5.5mV at BER = 10 ~ (-12) and the layout area is only 0.53 × 0.72mm because of no no passive inductor. The total gain is over 41 dB, and bandwidth exceeds 12 GHz with 56 mW power dissipation.